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april 2013 ? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 FDMF6708N ? extra-small, high-performa nce, high-freque ncy drmos module FDMF6708N ? extra-small, high-performance, high-frequency drmos module benefits ? ultra-compact 6x6 mm pqfn, 72% space-saving compared to conventional discrete solutions ? fully optimized system efficiency ? clean switching waveforms with minimal ringing ? high-current handling features ? over 93% peak-efficiency ? high-current handling: 50 a ? high-performance pqfn copper-clip package ? 3-state 5 v pwm input driver ? automatic diode emulation (skip mode) enabled through zcd_en# input ? thermal warning flag for over-temperature condition ? driver output disable function (disb# pin) ? internal pull-up and pull-down for zcd_en# and disb# inputs, respectively ? fairchild powertrench ? technology mosfets for clean voltage waveforms and reduced ringing ? fairchild syncfet? (integrated schottky diode) technology in low-side mosfet ? integrated bootstrap schottky diode ? adaptive gate drive timing for shoot-through protection ? under-voltage lockout (uvlo) ? optimized for switching frequencies up to 1mhz ? low-profile smd package ? fairchild green packaging and rohs compliance ? based on the intel ? 4.0 drmos standard description the xs? drmos family is fairchild?s next-generation, fully optimized, ultra-compact, integrated mosfet plus driver power stage solution for high-current, high- frequency, synchronous buck dc-dc applications. the FDMF6708N integrates a driver ic, two power mosfets, and a bootstrap schottky diode into a thermally enhanced, ultra-compact 6x6 mm package. with an integrated approach, the complete switching power stage is optimized with regard to driver and mosfet dynamic performanc e, system inductance, and power mosfet r ds(on) . xs? drmos uses fairchild's high-performance powertrench ? mosfet technology, which dramatically reduces switch ringing, eliminating the need for snubber circuit in most buck converter applications. a driver ic with reduced dead times and propagation delays further enhances the performance. a thermal warning function warns of a potential over-temperature situation. the FDMF6708N also incorporates a zero- cross detect (zcd_en#) for improved light-load efficiency. the FDMF6708N also provides a 3-state 5 v pwm input for compatibility with a wide range of pwm controllers. applications ? notebook computers ? high-performance gaming motherboards ? compact blade servers & workstations, v-core and non-v-core dc-dc converters ? desktop computers, v-core and non-v-core dc-dc converters ? high-current dc-dc point-of-load converters ? networking and telecom microprocessor voltage regulators ? small form-factor voltage regulator modules ordering information part number current rating package top mark FDMF6708N 50 a 40-lead, clipbond pqfn dr mos, 6.0 mm x 6.0 mm package FDMF6708N
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 2 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module typical application circuit v 5v disb# pwm input off on c vdrv c vin c boot r boot l out c out v in FDMF6708N open- drain output vdrv vcin vin pwm thwn# boot cgnd pgnd disb# phase smod# c vcin v out vswh 3v ~ 24v r vcin figure 1. typical application circuit drmos block diagram figure 2. drmos block diagram zcd_en# pwm vcin vdrv vin pgnd phase gh d boot boot gl cgnd disb# thwn# q1 hs power mosfet input 3- state logic r up_pwm v cin v cin uvlo gh logic level-shift dead-time control temp. sense 20k gl logic 10a 10a r dn_pwm q2 ls power mosfet vswh v drv
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 3 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module pin configuration figure 3. bottom view figure 4. top view pin definitions pin # name description 1 zcd_en# when zcd_en#=high, the low-side driver is the inverse of the pwm input. when zcd_en#=low, diode emulation is enabled. this pin has a 10 a internal pull-up current source. do not add a noise filter capacitor. 2 vcin ic bias supply. minimum 1 f ceramic ca pacitor is recommended from this pin to cgnd. 3 vdrv power for the gate driver. minimum 1 f cera mic capacitor is recommended to be connected as close as possible from this pin to cgnd. 4 boot bootstrap supply input. provides voltage supp ly to the high-side mosfet driver. connect a bootstrap capacitor from this pin to phase. 5, 37, 41 cgnd ic ground. ground return for driver ic. 6 gh for manufacturing test only. this pin must float; it must not be connected to any pin. 7 phase switch node pin for bootstrap capacitor r outing. electrically shorted to vswh pin. 8 nc no connect. the pin is not electrically connected internally, but can be connected to vin for convenience. 9 - 14, 42 vin power input. output stage supply voltage. 15, 29 - 35, 43 vswh switch node input. provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection. 16 ? 28 pgnd power ground. output stage groun d. source pin of the low-side mosfet. 36 gl for manufacturing test only. this pin must float; it must not be connected to any pin. 38 thwn# thermal warning flag, open collector output. w hen temperature exceeds the trip limit, the output is pulled low. thwn# does not disable the module. 39 disb# output disable. when low, this pin disables the power mosfet switching (gh and gl are held low). this pin has a 10 a internal pull-d own current source. do not add a noise filter capacitor. 40 pwm pwm signal input. this pin accepts a three-state 5 v pwm signal from the controller.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 4 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cin supply voltage referenced to cgnd -0.3 7.0 v v drv drive voltage referenced to cgnd -0.3 7.0 v v disb# output disable referenced to cgnd -0.3 7.0 v v pwm pwm signal input referenced to cgnd -0.3 7.0 v v zcd_en# zcd enable signal input referenced to cgnd -0.3 7.0 v v gl low gate manufacturing test pin referenced to cgnd -0.3 7.0 v v thwn# thermal warning flag referenced to cgnd -0.3 7.0 v v in power input referenced to pgnd, cgnd -0.3 30.0 v v boot bootstrap supply referenced to vswh, phase -0.3 7.0 v referenced to cgnd -0.3 30.0 v v gh high gate manufacturing test pin referenced to vswh, phase -0.3 7.0 v referenced to cgnd -0.3 30.0 v v phs phase referenced to cgnd -0.3 30.0 v v swh switch node input referenced to pgnd, cgnd (dc only) -0.3 30.0 v referenced to pgnd,<20 ns -8.0 33.0 v v boot bootstrap supply referenced to vdrv 22.0 v referenced to vdrv,<20 ns 25.0 v i thwn# thwn# sink current -0.1 7.0 ma i o(av) output current (1) f sw =300 khz, v in =12 v, v o =1.0 v 50 a f sw =1 mhz, v in =12 v, v o =1.0 v 45 jpcb junction-to-pcb thermal resistance 3.5 c/w t a ambient temperature range -40 +125 c t j maximum junction temperature +150 c t stg storage temperature range -55 +150 c esd electrostatic discharge protection human body model, jesd22-a114 2000 v charged device model, jesd22-c101 2500 note: 1. i o(av) is rated using fairchild?s drmos evaluation board, at t a = 25c, with natural convection cooling. this rating is limited by the peak drmos temperature, t j = 150c, and varies depending on operating conditions and pcb layout. this rating can be changed with different application settings . recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. typ. max. unit v cin control circuit supply voltage 4.5 5.0 5.5 v v drv gate drive circuit supply voltage 4.5 5.0 5.5 v v in output stage supply voltage 3.0 12.0 24.0 (2) v note: 2. operating at high v in can create excessive ac overshoots on the vswh-to-gnd and boot-to-gnd nodes during mosfet switching transient s. for reliable drmos operation, vswh-to-gnd and boot-to-gnd must remain at or below the absolute maximum ratings shown in the table above. refer to the ?application information? and ?pcb layou t guidelines? sections of this da tasheet for additi onal information .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 5 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module electrical characteristics typical values are v in = 12 v, v cin = 5 v, v drv = 5 v, and t a = t j = +25c unless otherwise noted. symbol parameter condition min. typ. max. unit basic operation i q quiescent current i q =i vcin +i vdrv , pwm=low or high or float 2 ma v uvlo uvlo threshold v cin rising 3.3 v v uvlo_hys uvlo hysteresis 0.35 v pwm input ( v cin = v drv = 5 v 10%) r up_pwm pull-up impedance v pwm =5 v 20 k ? r dn_pwm pull-down impedance v pwm =0 v 20 k ? v ih_pwm pwm high level voltage 3.15 3.80 4.45 v v tri_hi 3-state upper threshol d 3.10 3.75 4.40 v v tri_lo 3-state lower threshol d 1.05 1.40 1.90 v v il_pwm pwm low level voltage 0.70 1.00 1.30 v t d_hold-off 3-state shut-off time 150 ns v hiz_pwm 3-state open voltage 2.20 2.50 2.80 v t pwm-off_min pwm minimum off time 70 ns pwm input (v cin = v drv = 5 v 5%) r up_pwm pull-up impedance v pwm =5 v 20 k ? r dn_pwm pull-down impedance v pwm =0 v 20 k ? v ih_pwm pwm high level voltage 3.35 3.80 4.25 v v tri_hi 3-state upper threshol d 3.30 3.75 4.20 v v tri_lo 3-state lower threshol d 1.10 1.40 1.75 v v il_pwm pwm low level voltage 0.74 1.00 1.26 v t d_hold-off 3-state shut-off time 150 ns v hiz_pwm 3-state open voltage 2.30 2.50 2.70 v t pwm-off_min pwm minimum off time 70 ns disb# input v ih_disb high-level input voltage 2 v v il_disb low-level input voltage 0.8 v i pld pull-down current 10 a t pd_disbl propagation delay pwm=gnd, delay between disb# from high to low to gl from high to low 220 ns t pd_disbh propagation delay pwm=gnd, delay between disb# from low to high to gl from low to high 520 ns zcd_en# input v ih_zcd_en high-level input voltage 2 v v il_zcd_en low-level input voltage 0.8 v i plu pull-up current 10 a t pd_zlgll propagation delay pwm=gnd, delay between zcd_en# from high to low to gl from high to low 1800 ns t pd_zhglh propagation delay pwm=gnd, delay between zcd_en# from low to high to gl from low to high 20 ns continued on the following page?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 6 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module electrical characteristics typical values are v in = 12 v, v cin = 5 v, v drv = 5 v, and t a = t j = +25c unless otherwise noted. symbol parameter condition min. typ. max. unit thermal warning flag t act activation temperature 150 c t rst reset temperature 135 c r thwn pull-down resistance 5 k ? resistor pull-up to v cin 60 ? high-side driver (f sw = 1000 khz, i out = 30 a, t a = +25 c) r source_gh output impedance, sourcing source current=50 ma 0.8 ? r sink_gh output impedance, sinking sink current=50 ma 0.6 ? t r_gh rise time gh=10% to 90% 10 ns t f_gh fall time gh=90% to 10% 10 ns t d_deadon ls to hs deadband time gl going low to gh going high, 1.7 v gl to 10% gh 20 ns t pd_plghl pwm low propagation delay pwm going low to gh going low, v il_pwm to 90% gh 20 ns t pd_phghh pwm high propagation delay (zcd_en# =0) pwm going high to gh going high, v ih_pwm to 10% gh (zcd_en# =0, i d_ls >0) 25 ns t pd_tsghh exiting 3-state propagation delay pwm (from 3-state) going high to gh going high, v ih_pwm to 10% gh 35 ns low-side driver (f sw = 1000 khz, i out = 30 a, t a = +25 c) r source_gl output impedance, sourcing source current=50 ma 0.9 ? r sink_gl output impedance, sinking sink current=50 ma 0.4 ? t r_gl rise time gl=10% to 90% 20 ns t f_gl fall time gl=90% to 10% 10 ns t d_deadoff hs to ls deadband time sw going low to gl going high, 1.7 v sw to 10% gl 20 ns t pd_phgll pwm-high propagation delay pwm going high to gl going low, v ih_pwm to 90% gl 20 ns t pd_tsglh exiting 3-state propagation delay pwm (from 3-state) going low to gl going high, v il_pwm to 10% gl 30 ns t gl-on_min gl minimum on time in dcm v zcd_en# =0 v 350 ns boot diode v f forward-voltage drop i f =1 ma 0.6 v v r breakdown voltage i r =1 ma 22 v
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 7 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module figure 5. pwm timing diagram t d_deadon pwm vswh gh to vswh gl t pd phgll t d _ deadoff v ih _ pwm v il _ pwm 90% 90% 1.7v 10% t pd plghl 10% 1.7v
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 8 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module typical performance characteristics test conditions: v in =12 v or 19 v, v out =1 v, v cin =5 v, v drv =5 v, l out =250 nh, t a =25c, and natural convection cooling, unless otherwise specified. figure 6. safe operating area for 12 v in figure 7. safe operating area for 19 v in figure 8. power loss vs. output current for 12 v in figure 9. power loss vs. output current for 19 v in figure 10. power loss vs. switching frequency figure 11. power loss vs. input voltage 0 5 10 15 20 25 30 35 40 45 50 0 25 50 75 100 125 150 module output current, i out (a) pcb temperature, t pcb (c) f sw = 300khz f sw = 1000khz v in = 12v, v drv & v cin = 5v, v out = 1v 0 5 10 15 20 25 30 35 40 45 50 0 25 50 75 100 125 150 module output current, i out (a) pcb temperature, t pcb ( c) f sw = 300khz f sw = 1000khz v in = 19v, v drv & v cin = 5v, v out = 1v 0 1 2 3 4 5 6 7 8 9 10 11 0 5 10 15 20 25 30 35 40 45 module power loss, pl mod (w) module output current, i out (a) 12vin 300khz 12vin 500khz 12vin 800khz 12vin 1000khz v drv & v cin = 5v, v out = 1v 0 1 2 3 4 5 6 7 8 9 10 11 0 5 10 15 20 25 30 35 40 45 module power loss, pl mod (w) module output current, i out (a) 19vin 300khz 19vin 500khz 19vin 800khz 19vin 1000khz v drv & v cin = 5v, v out = 1v 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 100 200 300 400 500 600 700 800 900 1000 1100 normalized module power loss module switching frequency, f sw (khz) v in = 12v, v drv & v cin = 5v, v out = 1v, i out = 30a 0.96 1.00 1.04 1.08 1.12 1.16 4 6 8 10 12 14 16 18 20 normalized module power loss module input voltage, v in (v) v drv & v cin = 5v, v out = 1v, f sw = 300khz, i out = 30a
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 9 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module typical performance characteristics test conditions: v in =12 v, v out =1 v, v cin =5 v, v drv =5 v, l out =250 nh, t a =25c, and natural convection cooling, unless otherwise specified. figure 12. power loss vs. driver supply voltage figure 13. power loss vs. output voltage figure 14. power loss vs. output inductor figure 15. driver supply current vs. switching frequency figure 16. driver supply current vs. driver supply voltage figure 17. driver supply current vs. output current 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 4.0 4.5 5.0 5.5 6.0 normalized module power loss driver supply voltage, v drv & v cin (v) v in = 12v, v out = 1v, f sw = 300khz, i out = 30a 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 normalized module power loss module output voltage, v out (v) v in = 12v, v drv & v cin = 5v, f sw = 300khz, i out = 30a 0.96 0.97 0.98 0.99 1.00 1.01 200 250 300 350 400 450 500 normalized module power loss output inductor, l out (nh) v in = 12v, v drv & v cin = 5v, f sw = 300khz, v out = 1v, i out = 30a 5 10 15 20 25 30 35 40 45 100 200 300 400 500 600 700 800 900 1000 1100 driver supply current, i drv & i cin (ma) module switching frequency, f sw (khz) v in = 12v, v drv & v cin = 5v, v out = 1v, i out = 0a 8 9 10 11 12 13 14 4.0 4.5 5.0 5.5 6.0 driver supply current, i drv & i cin (ma) driver supply voltage, v drv & v cin (v) v in = 12v, v out = 1v, f sw = 300khz, i out = 0a 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 0 5 10 15 20 25 30 35 40 45 normalized driver supply current module output current, i out (a) v in = 12v, v drv & v cin = 5v, v out = 1v f sw = 300khz f sw = 1000khz
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 10 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module typical performance characteristics test conditions: v cin =5 v, v drv =5 v, t a =25c, and natural convection cooli ng, unless otherwise specified. figure 18. uvlo threshold vs. te mperature figure 19. pwm thres hold vs. driver supply voltage figure 20. pwm threshold vs. temperature fi gure 21. zcd_en# threshold vs. driver supply voltage figure 22. zcd_en# threshold vs. temperature figure 23. zcd_en# pull-up current vs. temperature 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 -55 0 25 55 100 125 150 driver supply voltage, v cin (v) driver ic junction temperature, t j ( o c) uvlo up uvlo dn 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.50 4.75 5.00 5.25 5.50 pwm threshold voltage, v pwm (v) driver supply voltage, v cin (v) v ih_pwm t a = 25 c v tri_hi v tri_lo v il_pwm v hiz_pwm 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -55 0 25 55 100 125 150 pwm threshold voltage, v pwm (v) driver ic junction temperature, t j ( o c) v cin = 5v v ih_pwm v tri_hi v hiz_pwm v tri_lo v il_pwm 1.0 1.2 1.4 1.6 1.8 2.0 4.50 4.75 5.00 5.25 5.50 zcd_en# threshold voltage, v zcd_en# (v) driver supply voltage, v cin (v) v ih_zcd_en# v il_zcd_en# t a = 25 c 1.2 1.3 1.4 1.5 1.6 1.7 1.8 -55 0 25 55 100 125 150 zcd_en# threshold voltage, v zcd_en# (v) driver ic junction temperature, t j ( o c) v ih_zcd_en# v il_zcd_en# v cin = 5v -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -55 0 25 55 100 125 150 zcd_en# pull-up current, i plu (ua) driver ic junction temperature, t j ( o c) v cin = 5v
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 11 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module typical performance characteristics test conditions: v cin =5 v, v drv =5 v, t a =25c, and natural convection cooli ng, unless otherwise specified. figure 24. disb# threshold vs. driver supply voltage figure 25. disb# threshold vs. temperature figure 26. disb# pull-down current vs. temperature figure 27. boot diode forward voltage vs. temperature 1.0 1.2 1.4 1.6 1.8 2.0 4.50 4.75 5.00 5.25 5.50 disb# threshold voltage, v disb# (v) driver supply voltage, v cin (v) v ih_disb# v il_disb# t a = 25 c 1.2 1.3 1.4 1.5 1.6 1.7 1.8 -55 0 25 55 100 125 150 disb# threshold voltage, v disb# (v) driver ic junction temperature, t j ( o c) v ih_disb# v il_disb# v cin = 5v 7 8 9 10 11 12 13 14 -55 0 25 55 100 125 150 disb# pull-down current, i pld (ua) driver ic junction temperature, t j ( o c) v cin = 5v 300 350 400 450 500 550 600 650 700 -55 0 25 55 100 125 150 boot diode forward voltage, v f (mv) driver ic junction temperature, t j ( o c) i f = 1ma
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 12 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module functional description the FDMF6708N is a driver-plus-fet module optimized for the synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high-side and the low-side mosfets. each part is capable of driving speeds up to 1 mhz. vcin and disable (disb#) the vcin pin is monitored by an under-voltage lockout (uvlo) circuit. when v cin rises above ~3.3 v, the driver is enabled. when v cin falls below ~2.95 v, the driver is disabled (gh, gl=0). the driver can also be disabled by pulling the disb# pin low (disb# < v il_disb ), which holds both gl and gh low regardless of the pwm input state. the driver can be enabled by raising the disb# pin voltage high (disb# > v ih_disb ). table 1. uvlo and disable logic uvlo disb# driver state 0 x disabled (gh, gl=0) 1 0 disabled (gh, gl=0) 1 1 enabled ( see table 2 ) 1 open disabled (gh, gl=0) note: 3. disb# internal pull-down current source is 10 a. thermal warning flag (thwn#) the FDMF6708N provides a thermal warning flag (thwn#) to warn of over-temperature conditions. the thermal warning flag uses an open-drain output that pulls to cgnd when the activation temperature (150c) is reached. the thwn# output returns to a high- impedance state once the temperature falls to the reset temperature (135c). for use, the thwn# output requires a pull-up resistor, which can be connected to vcin. thwn# does not disable the drmos module. figure 28. thwn operation three-state pwm input the FDMF6708N incorporates a three-state 5 v pwm input gate drive design. the three-state gate drive has both logic high level and low level, along with a three-state shutdown window. when the pwm input signal enters and remains within the three-state window for a defined hold-off time (t d_hold-off ), both gl and gh are pulled low. this enables the gate drive to shut down both high-side and low-side mosfets to support features such as phase shedding, which is common on multi-phase voltage regulators. exiting three-state condition when exiting a valid thr ee-state condition, the FDMF6708N follows the pwm input command. if the pwm input goes from three-state to low, the low-side mosfet is turned on. if the pwm input goes from three-state to high, the high-side mosfet is turned on. this is illustrated in figure 29. the FDMF6708N design allows for short propagation delays when exiting the three-state window (see electrical characteristics) . low-side driver the low-side driver (gl) is designed to drive a ground- referenced, low-r ds(on) , n-channel mosfet. the bias for gl is internally connected between the vdrv and cgnd pins. when the driver is enabled, the driver's output is 180 out of phase with the pwm input. when the driver is disabled (disb#=0v), gl is held low. high-side driver the high-side driver (gh) is designed to drive a floating n-channel mosfet. the bias voltage for the high-side driver is developed by a bootstrap supply circuit consisting of the internal schottky diode and external bootstrap capacitor (c boot ). during startup, v swh is held at pgnd, allowing c boot to charge to v drv through the internal diode. when the pwm input goes high, gh begins to charge the gate of the high-side mosfet (q1). during this transition, the charge is removed from c boot and delivered to the gate of q1. as q1 turns on, v swh rises to v in , forcing the boot pin to v in + v boot , which provides sufficient v gs enhancement for q1. to complete the switching cycle, q1 is turned off by pulling gh to v swh . c boot is then recharged to v drv when v swh falls to pgnd. gh output is in-phase with the pwm input. the high-side gate is held low when the driver is disabled or the pwm signal is held within the three-state window for longer than the three-state hold-off time, t d_hold-off . 150c a ctivation tem p e r ature t j_driver ic thermal warning normal operation high low 135c reset temperature thwn# logic state
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 13 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module adaptive gate drive circuit the driver ic advanced design ensures minimum mosfet dead-time, while eliminating potential shoot- through (cross-conduction) curr ents. it senses the state of the mosfets and adjusts the gate drive adaptively to ensure they do not conduct simultaneously. figure 29 provides the relevant timing waveforms. to prevent overlap during the low-to-high switching transition (q2 off to q1 on), the adapti ve circuitry monitors the voltage at the gl pin. when the pwm signal goes high, q2 begins to turn off after a propagation delay (t pd_phgll ). once the gl pin is discharged below 1.7 v, q1 begins to turn on after adaptive delay t d_deadon . to preclude overlap during the high-to-low transition (q1 off to q2 on), the adapti ve circuitry monitors the voltage at the gh-to-phase pin pair. when the pwm signal goes low, q1 begins to turn off after a propagation delay (t pd_plghl ). once the voltage across gh-to-phase falls below 1.7 v, q2 begins to turn on after adaptive delay t d_deadoff . figure 29. pwm and 3-statetiming diagram t pd _ tsghh vswh gh to vswh gl t pd_phgll t d _ hold-off 90% less than t d_hold-off exit 3- state 1.7 v pwm v il pwm v ih_pwm v tri_hi v ih_pwm v ih_pwm 10% t r _ gl t d_hold-off t pd_tsglh less than t d _ hold-off exit 3-state v ih_pwm v tri_hi v tri_lo v il_pwm t pd _ plghl t pd_tsghh dcm t f_gh t r_gh t d_hold-off 10% ccm dcm exit 3-state 90% 1 0% 90% enter 3 -state enter 3 -state t d _ deadoff t d_deadon enter 3 - state t f_gl v in v out 1.7 v notes: t pd_xxx = propagation delay from external signal (pwm, zcd_en#, etc.) to ic generated signal. example (t pd_phgll ? pwm going high to ls vgs (gl) going low) t d_xxx = delay from ic generated signal to ic generated signal. example (t d_deadon ? ls vgs (gl) low to hs vgs (gh) high) pwm exiting 3-state t pd_phgll = pwm rise to ls v gs fall, v ih_pwm to 90% ls v gs t pd_tsghh = pwm 3-state to high to hs v gs rise, v ih_pwm to 10% hs v gs t pd_plghl = pwm fall to hs v gs fall, v il_pwm to 90% hs v gs t pd_tsglh = pwm 3-state to low to ls v gs rise, v il_pwm to 10% ls v gs t pd_phghh = pwm rise to hs v gs rise, v ih_pwm to 10% hs v gs (zcd_en# held low) zcd_en# dead times t pd_zlgll = zcd_en# fall to ls v gs fall, v il_zcd_en to 90% ls v gs t d_deadon = ls v gs fall to hs v gs rise, ls-comp trip value (~1.7v gl) to 10% hs v gs t pd_zhglh = zcd_en# rise to ls v gs rise, v ih_zcd_en to 10% ls v gs t d_deadoff = vswh fall to ls v gs rise, sw-comp trip value (~1.7v vswh) to 10% ls v gs
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 14 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module zero cross detection mode (zcd_en#) the zero current detection mode allows for higher converter efficiency when operating in light-load conditions. when zcd_en# is pulled low; the low-side mosfet gate signal pulls low when internal circuitry detects positive ls mosfet drain current, preventing discharge of the output capacit ors as the filter inductor current attempts reverse current flow ? known as ?diode emulation? mode. when the zcd_en# pin is pulled high, the synchronous buck converter works in synchronous mode. this mode allows for gating of the low-side mosfet. when the zcd_en# pin is pulled low, the low-side mosfet is gated off automatically during positive ls mosfet drain current. if the zcd_en# pin is pulled low by the pwm controller to support light-load power- saving mode, FDMF6708N can actively turn off the low- side mosfet when it detects the zero crossing of the inductor current. the low-side mosfet turns on when inductor current is positive (ls mosfet drain current is negative) and turns off when inductor current is negative (ls mosfet drain current is positive). zero-crossing detection of the inductor current and low-side mosfet on and off are automatically performed on a cycle-by- cycle basis. normally this pin is active low. see figure 30 for timing delays. table 2. zcd_en# logic disb# pwm zcd_en# gh gl 0 x x 0 0 1 3-state x 0 0 1 0 0 0 0 (i l <0),1 (i l > 0) (4) 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 note: 4. gl = 0, when i l < 0 (inductor current is negative and flowing in to the drmos vswh node). gl = 1 when i l > 0 (inductor current is positive and flowing out of the drmos vswh node). figure 30. zcd_en# timing diagram t d_deadon pwm vswh gh to v swh gl t pd_phgll t pd_plghl t d_deadoff v ih_pwm v il_pwm 90% 90% 1.7v 1.7v t pd _ zhglh delay from zcd_en# going high to ls v gs high zcd_en# delay from zcd_en# going low to ls v gs low dcm (i l = 0) i l > 0 10% v out v ih_zcd_en v il_zcd_en dcm v il_zcd_en t pd_zlgll 90% 1 0% v ih_pwm 1 0% t pd_phgll i l < 0 detected and gl transitions low.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 15 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module application information supply capacitor selection for the supply inputs (v cin ), a local ceramic bypass capacitor is recommended to reduce noise and to supply the peak current. use at least a 1 f x7r or x5r capacitor. keep this capacitor close to the vcin pin and connect it to the gnd plane with vias. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c boot ), as shown in figure 32. a bootstrap capacitance of 100 nf x7r or x5r capacitor is usually adequate. a series bootstrap resistor may be needed for specific applications to improve switching noise immunity. the boot resistor may be required when operating above 15 v in and is effective at controlling the high-side mosfet turn-on slew rate and v shw overshoot. r boot values from 0.5 to 3.0 ? are typically effective in reducing vswh overshoot. vcin filter the vdrv pin provides powe r to the gate drive of the high-side and low-side power mosfet. in most cases, it can be connected directly to vcin, the pin that provides power to the logic section of the driver. for additional noise immunity, an rc filter can be inserted between the vdrv and vcin pins. recommended values would be 10 ? and 1 f. power loss and efficiency measurement and calculation refer to figure 32 for power loss testing method. power loss calculations are: p in =(v in x i in ) + (v 5v x i 5v ) (w) (1) p sw =v sw x i out (w) (2) p out =v out x i out (w) (3) p loss_module =p in - p sw (w) (4) p loss_board =p in - p out (w) (5) eff module =100 x p sw /p in (%) (6) eff board =100 x p out /p in (%) (7) figure 31. block diagram with v cin filter figure 32. power loss measurement
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 16 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module pcb layout guidelines figure 33 and figure 34 provide an example of a proper layout for the FDMF6708N and critical components. all of the high-current paths, su ch as vin, vswh, vout, and gnd copper, should be short and wide for low inductance and resistance. this aids in achieving a more stable and evenly distributed current flow, along with enhanced heat radiati on and system performance. recommendations for pcb designers 1. input ceramic bypass capacitors must be placed close to the vin and pgnd pins. this helps reduce the high-current power loop inductance and the input current ripple induced by the power mosfet switching operation. 2. the v swh copper trace serves two purposes. in addition to being the hi gh-frequency current path from the drmos package to the output inductor, it serves as a heat sink for the low-side mosfet in the drmos package. the trace should be short and wide enough to present a low-impedance path for the high-frequency, high- current flow between the drmos and inductor. the short and wide trace minimizes electrical losses as well as the drmos temperature rise. note that the v swh node is a high- voltage and high-frequency switching node with high noise potential. care should be taken to minimize coupling to adjacent traces. since this copper trace acts as a heat sink for the lower mosfet, balance using the largest area possible to improve drmos cooling while maintaining acceptable noise emission. 3. an output inductor should be located close to the FDMF6708N to minimize the power loss due to the v swh copper trace. care should also be taken so the inductor dissipation does not heat the drmos. 4. powertrench ? mosfets are used in the output stage and are effective at minimizing ringing due to fast switching. in most cases, no vswh snubber is required. if a snubber is used, it should be placed close to the vswh and pgnd pins. the selected resistor and capacitor need to be the proper size for power dissipation. 5. vcin, vdrv, and boot capacitors should be placed as close as possible to the vcin-to-cgnd, vdrv-to-cgnd, and boot-to-phase pin pairs to ensure clean and stable power. routing width and length should be considered as well. 6. include a trace from the phase pin to the vswh pin to improve noise margin. keep this trace as short as possible. 7. the layout should include the option to insert a small-value series boot resistor between the boot capacitor and boot pin. the boot-loop size, including r boot and c boot , should be as small as possible. the boot resistor may be required when operating above 15 v in and is effective at controlling the high-side mosfet turn-on slew rate and v shw overshoot. r boot can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative v swh ringing. inserting a boot resistance lowers the drmos efficiency. efficiency versus noise trade-offs must be considered. r boot values from 0.5 to 3.0 are typically effective in reducing v swh overshoot. 8. the vin and pgnd pins handle large current transients with frequency components greater than 100 mhz. if possible, these pins should be connected directly to the vin and board gnd planes. the use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. this added inductance in series with either the vin or pgnd pin degrades system noise immunity by increasing positive and negative v swh ringing. 9. gnd pad and pgnd pins should be connected to the gnd copper plane with multiple vias for stable grounding. poor grounding can create a noise transient offset voltage level between cgnd and pgnd. this could lead to f aulty operation of the gate driver and mosfets. 10. ringing at the boot pin is most effectively controlled by close placem ent of the boot capacitor. do not add an additional boot to the pgnd capacitor. this may lead to excess current flow through the boot diode. 11. the zcd_en# and disb# pins have weak internal pull-up and pull-down current sources, respectively. these pins should not have any noise filter capacitors. do not to float these pins unless absolutely necessary. 12. use multiple vias on the vin and vout copper areas to interconnect top, inner, and bottom layers to distribute current flow and heat conduction. do not put many vias on the vswh copper to avoid extra parasitic inductance and noise on the switching waveform. as long as efficiency and thermal performance are acceptable, place only one vswh copper on the top layer and use no vias on the vswh copper to minimize switch node parasitic noise. vias should be relatively large and of reasonably low induc tance. critical high- frequency components, such as r boot , c boot , rc snubber, and bypass capacitors; should be located as close to the respective drmos module pins as possible on the top layer of the pcb. if this is not feasible, they can be connected from the backside through a network of low-inductance vias.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 17 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module figure 33. pcb layout example (top view) figure 34. pcb layout example (bottom view)
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 18 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module physical dimensions figure 35. 40-lead, clipbond pq fn drmos, 6.0x6.0 mm package package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . bottom view land pattern recommendation notes: unless ot herwise specified a) does not fully conform to jedec registration mo-220, dated may/2005. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. mold flash or burrs does not exceed 0.10mm. d) dimensioning and tolerancing per asme y14.5m-1994. e) drawing file name: pqfn40arev3 see detail 'a' detail 'a' scale: 2:1 seating plane 0.65 0.40 2.10 0.50 typ 4.50 5.80 2.50 0.25 1.60 0.60 0.15 2.10 0.35 1 top view front view c 0.30 0.20 0.05 0.00 1.10 0.90 0.10 c 0.08 c 10 11 20 21 30 31 40 0.40 0.50 (0.70) 0.40 2.000.10 2.000.10 (0.20) (0.20) 1.500.10 0.50 0.30 (40x) 0.20 6.00 6.00 0.10 c 2x b a 0.10 c 2x 0.30 0.20 (40x) 4.400.10 0.10 cab 0.05 c (2.20) 0.50 10 1 40 31 30 21 20 11 pin#1 indicator pin #1 indicator may appear as optional 2.400.10
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6708N ? rev. 1.0.3 19 FDMF6708N ? extra-small, high-perfo rmance, high-freque ncy drmos module
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